Affiliation:
1. Graduate School of Information Science, Hiroshima City University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Reference14 articles.
1. [1] S. Wang, X. Liu, and S.T. Chakradhar, “Hybrid delay scan: A low hardware overhead scan-based delay test technique for high fault coverage and compact test sets,” Proc. Design, Automation and Test in Europe, pp.1296-1301, 2004.
2. [2] A. Krstic and K.T. Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Academic Publishers, 1998.
3. Scan-based transition test
4. Broad-side delay test
5. [5] R. Adapa, E. Flanigan, and S. Tragoudas, “Function-based test generation for (non-robust) path delay faults using the launch-off-capture scan architecture,” Proc. International Symp. on Quality Electronic Design, pp.717-722, 2007.