An Integrated Framework for Energy Optimization of Embedded Real-Time Applications-Reference-Cited by-同舟云学术

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications

Published:2014 Issue:12 Volume:E97.A Page:2477-2487
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

TAKASE Hideki¹,ZENG Gang¹,GAUTHIER Lovic²,KAWASHIMA Hirotaka¹,ATSUMI Noritoshi¹,TATEMATSU Tomohiro¹,KOBAYASHI Yoshitake³,KOSHIRO Takenori³,ISHIHARA Tohru²,TOMIYAMA Hiroyuki⁴,TAKADA Hiroaki¹

Affiliation:

1. Graduate School of Information Science, Nagoya University

2. System LSI Research Center, Kyushu University

3. Toshiba Corporation

4. College of Science and Engineering, Ritsumeikan University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E97.A/12/E97.A_2477/_pdf

Reference23 articles.

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2. [2] L. Gauthier and T. Ishihara, “Implementation of stack data placement and run time management using a scratch-pad memory for energy consumption reduction of embedded applications,” IEICE Trans. Fundamentals, vol.E94-A, no.12, pp.2597-2608, Dec. 2011.

3. [3] P. Bjuréus and A. Jantsch, “Performance analysis with confidence intervals for embedded software processes,” Proc. 14th International Symposium on Systems Synthesis, ISSS '01, pp.45-50, New York, NY, USA, 2001.

4. [4] G. Zeng, H. Tomiyama, and H. Takada, “A generalized framework for energy savings in hard real-time embedded systems,” IPSJ Trans. System LSI Design Methodology, vol.2, pp.167-179, Aug. 2009.

5. [5] W. Kim, D. Shin, H.S. Yun, J. Kim, and S.L. Min, “Performance evaluation of dynamic voltage scaling algorithms for hard real-time systems,” J. Low Power Electronics, vol.1, no.3, pp.207-216, 2005.

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