SLM: A Scalable Logic Module Architecture with Less Configuration Memory

Author:

AMAGASAKI Motoki1,ARAKI Ryo1,IIDA Masahiro1,SUEYOSHI Toshinori1

Affiliation:

1. Graduate School of Science and Technology, Kumamoto University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks;2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS);2024-04-17

2. An eFPGA Generation Suite with Customizable Architecture and IDE;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2023-03-01

3. FPGA for secured hardware & IP ownership;2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON);2022-11-26

4. FPL Demo: An FPGA-IP Prototype Chip for MEC devices;2022 32nd International Conference on Field-Programmable Logic and Applications (FPL);2022-08

5. ROUTING RESOURCES REDUCTION OF VIRTUAL FPGA FOR SPECIFIC APPLICATION SETS;INT J INNOV COMPUT I;2020

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