COGRE: A Novel Compact Logic Cell Architecture for Area Minimization-Reference-Cited by-同舟云学术

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

Published:2012 Issue:2 Volume:E95-D Page:294-302
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

IIDA Masahiro¹,AMAGASAKI Motoki¹,OKAMOTO Yasuhiro¹,ZHAO Qian¹,SUEYOSHI Toshinori¹

Affiliation:

1. Graduate School of Science and Technology, Kumamoto University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

http://www.jstage.jst.go.jp/article/transinf/E95.D/2/E95.D_2_294/_pdf

Reference24 articles.

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2. [2] T. Sueyoshi and M. Iida, “Configurable and reconfigurable computing for digital signal processing,” IEICE Trans. Fundamentals, vol.E85-A, no.3, pp.591-599, March 2002.

3. [3] Actel, Application Note: Introduction to Actel FPGA Architecture, 1997.

4. [4] QuickLogic Corp., Eclipse II Family Data Sheet, 2004.

5. [5] M. Amagasaki, R. Yamaguchi, M. Koga, M. Iida, and T. Sueyoshi, “An embedded reconfigurable IP core with variable grain logic cell architecture,” International Journal of Reconfigurable Computing, vol.2008, Article ID 180216, p.14, 2008.

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