Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming

Author:

DONG Qing1,YANG Bo1,LI Jing1,NAKATAKE Shigetoshi1

Affiliation:

1. Department of Information and Media Engineering, The University of Kitakyushu

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference11 articles.

1. [1] J. Cong and M. Sarrafzadeh, “Incremental physical design, ” ISPD'00: Proc. 2000 International Symposium on Physical Design, pp.34-42, 2000.

2. [2] S. Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, and J. Gu, “A buffer planning algorithm based on dead space redistribution, ” ASP-DAC'03: Proc. 2003 Conference on Asia South Pacific Design Automation, pp.435-438, 2003.

3. [3] Y.H. Cheng and Y.W. Chang, “Integrating buffer planning with floorplanning for simultaneous multi-objective optimization, ” ASP-DAC'04: Proc. 2003 Conference on Asia South Pacific Design Automation, pp.624-627, 2004.

4. [4] S. Adya, I. Markov, and P. Villarrubia, “On whitespace and stability in mixed-size placement and physical synthesis, ” Proc. Int. Conf. on Computer Aided Design, pp.311-318, 2003.

5. [5] C. Li, M. Xie, C.K. Koh, J. Cong, and P.H. Madden, “Routability-driven placement and white space allocation, ” Proc. Int. Conf. on Computer Aided Design, pp.394-401, 2004.

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2013

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