Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning-Reference-Cited by-同舟云学术

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Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning

Published:2013 Issue:12 Volume:E96.A Page:2467-2474
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

LI Katherine Shu-Min¹,HO Yingchieh²,CHEN Liang-Bi¹

Affiliation:

1. Department of Computer Science and Engineering, National Sun Yat-Sen University

2. Department of Electrical Engineering, National Dong-Hwa University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/12/E96.A_2467/_pdf

Reference22 articles.

1. [1] Semiconductor Industry Association, National Technology Road-map for Semiconductors 1999 Edition, Nov. 1999.

2. [2] C.J. Alpert and A. Devgan, “Wire segmenting for improved buffer insertion,” Proc. DAC, pp.588-593, 1997.

3. [3] J. Cong, T. Kong, and D.Z. Pan, “Buffer block planning for interconnect-driven floorplanning,” Proc. ICCA, pp.358-363, 1999.

4. [4] J. Cong, T. Kong, and, D.Z. Pan, “Buffer block planning for interconnect planning and prediction,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.9, no.6, pp.929-937, 2001.

5. [5] P. Sarkar and C.K. Koh, “Routability-driven repeater block planning for interconnect-centric floorplanning,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.20, no.5, pp.660-671, 2001.

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