Floorplanning for High Utilization of Heterogeneous FPGAs-Reference-Cited by-同舟云学术

Floorplanning for High Utilization of Heterogeneous FPGAs

Published:2012 Issue:9 Volume:E95.A Page:1529-1537
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

LIU Nan¹,CHEN Song¹,YOSHIMURA Takeshi¹

Affiliation:

1. Graduate School of IPS, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E95.A/9/E95.A_1529/_pdf

Reference13 articles.

1. [1] M. Wang, A. Ranjan, and S. Raje, “Multi-million gate FPGA physical design challenges,” Proc. ICCAD, pp.891-898, Nov. 2003.

2. [3] R. H. J. M. Otten, “Automatic floorplan design,” Proc. IEEE/ACM Design Automation Conference, pp.261-267, June 1982.

3. [4] L.J. Stockmeyer, “Optimal orientations of cells in slicing floorplan designs,” Inf. Control, vol.57, no.2/3, pp.91-101, May/June 1983.

4. [6] J. Yuan, S.Q. Dong, X.L. Hong, and Y.L. Wu, “LFF algorithm for heterogeneous FPGA floorplanning,” Proc. IEEE/ACM ASP-DAC, pp.1123-1126, Jan. 2005.

5. [7] Y. Feng and D.P. Mehta, “Heterogeneous floorplanning for FPGAs,” Proc. Int. Conf. VLSI Des., pp.257-262, Jan. 2006.

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