Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs-Reference-Cited by-同舟云学术

Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs

Published:2013 Issue:4 Volume:E96.C Page:501-510
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

LIU Nan¹,CHEN Song¹,YOSHIMURA Takeshi¹

Affiliation:

1. Graduate School of IPS, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E96.C/4/E96.C_501/_pdf

Reference28 articles.

1. [1] N. Liu, S. Chen, and T. Yoshimura, “Floorplanning for high utilization of heterogeneous FPGAs,” IEICE Trans. Fundamentals, vol.E95-A, no.9, pp.1529-1537, Sept. 2012.

2. [2] Xilinx Inc. [Online]. Available: http://www.xilinx.com

3. [3] S.P. Fekete, T. Kamphans, N. Schweer, C. Tessars, J.C. vanderVeen, J. Angermeier, D. Koch, and J. Teich, “Dynamic defragmentation of reconfigurable devices,” ACM Trans. Reconfigurable Technol. Syst., vol.5, no.2, article 7, June 2012.

4. [4] A. Kahoul, A.M. Smith, G.A. Constantinides, and P.Y.K. Cheung, “Efficient heterogeneous architecture floorplan optimization using analytical methods,” ACM Trans. Reconfigurable Technol. Syst., vol.5, no.2, article 3, Dec. 2010.

5. [5] L. Cheng and M.D.F. Wong, “Floorplan design for multimillion gate FPGAs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.25, no.12, pp.2795-2805, Dec. 2006.

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