MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop-Reference-Cited by-同舟云学术

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MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop

Published:2019-07-01 Issue:7 Volume:E102.A Page:867-877
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

MASUDA Yutaka¹,HASHIMOTO Masanori¹

Affiliation:

1. Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E102.A/7/E102.A_867/_pdf

Reference24 articles.

1. [1] B. Zhang and M. Orshansky, “Modeling of NBTI-induced PMOS degradation under arbitrary dynamic temperature variation,” Proc. International Symposium on Quality Electronic Design, pp.774-779, March 2008. 10.1109/isqed.2008.4479836

2. [2] T. Wang and Q. Xu, “On the simulation of NBTI-induced performance degradation considering arbitrary temperature and voltage variations,” Proc. Design Automation Conference, pp.1-6, June 2014. 10.1145/2593069.2593170

3. [3] S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, “A self-tuning DVS processor using delay-error detection and correction,” IEEE J. Solid-State Circuits, vol.41, no.4, pp.792-804, April 2006. 10.1109/jssc.2006.870912

4. [4] K.A. Bowman, J.W. Tschanz, S.L. Lu, P.A. Aseron, M.M. Khellah, A. Raychowdhury, B.M. Geuskens, C. Tokunaga, C.B. Wilkerson, T. Karnik, and V.K. De, “A 45nm resilient microprocessor core for dynamic variation tolerance,” IEEE J Solid-State Circuits, vol.46, no.1, pp.194-208, Jan. 2011. 10.1109/jssc.2010.2089657

5. [5] M. Fojtik, D. Fick, Y. Kim, N. Pinckney, D.M. Harris, D. Blaauw, and D. Sylvester, “Bubble razor: Eliminating timing margins in an ARM Cortex-M3 processor in 45nm CMOS using architecturally independent error detection and correction,” IEEE J. Solid-State Circuits, vol.48, no.1, pp.66-81, Jan. 2013. 10.1109/jssc.2012.2220912

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1. BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC;Electronics;2023-11-30

2. Activation-aware Slack Assignment Based Mode-wise Voltage Scaling for Energy Minimization;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2021

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