Layer-Aware 3D-IC Partitioning for Area-Overhead Reduction Considering the Power of Interconnections and Pads-Reference-Cited by-同舟云学术

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Layer-Aware 3D-IC Partitioning for Area-Overhead Reduction Considering the Power of Interconnections and Pads

Published:2016 Issue:6 Volume:E99.A Page:1206-1215
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

LAI Yung-Hao¹,CHANG Yang-Lang¹,FANG Jyh-Perng¹,CHANG Lena²,KOBAYASHI Hirokazu³

Affiliation:

1. Department of Electrical Engineering, National Taipei University of Technology

2. Department of Communications, Navigation and Control Engineering, National Taiwan Ocean University

3. Department of Electrics, Information and Communication Engineering, Osaka Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E99.A/6/E99.A_1206/_pdf

Reference26 articles.

1. [1] International Technology Roadmap for Semiconductor, Semiconductor Industry Association, 2009.

2. [2] K. Banerjee, S.J. Souri, P. Kapur, and K.C. Saraswat, “3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration,” Proc. IEEE, vol.89, no.5, pp.602-633, 2001.

3. [3] A.W. Topol, D.C. La Tulipe, L. Shi, D.J. Frank, K. Bernstein, S.E. Steen, A. Kumar, G.U. Singco, A.M. Young, K.W. Guarini, and M. Ieong, “Three-dimensional integrated circuits,” IBM J. Res. Dev., vol.50, no.4.5, pp.491-506, July/Sept. 2006.

4. [4] P. Garrou, C. Bower, and P. Ramm, Handbook of 3D integration: Technology and Applications of 3D Integrated Circuits, Wiley-VCH, 2008.

5. [5] C. Ferri, S. Reda, and R.I. Bahar, “Parametric yield management for 3D ICs: Models and strategies for improvement,” J. Emerg. Technol. Comput. Syst., vol.4, no.4, pp.1-22, Oct. 2008.

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