A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment-Reference-Cited by-同舟云学术

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment

Published:2010 Issue:7 Volume:E93-A Page:1319-1328
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

STEFAN DEVLIN Benjamin¹,NAKURA Toru²,IKEDA Makoto¹²,ASADA Kunihiro¹²

Affiliation:

1. Dept. of Electrical Engineering and Information Systems, The University of Tokyo

2. VLSI Design and Education Center (VDEC), The University of Tokyo

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E93.A/7/E93.A_7_1319/_pdf

Reference22 articles.

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2. [2] Q.T. Ho, J. Rigaud, L. Fesquet, M. Renaudin, and R. Rolland, “Implementing asynchronous circuits on LUT based FPGAs, ” Proc. Int'l Conf. Field Programmable Logic and Applications, Sept. 2002.

3. [3] J. Xin and R. Vemuri, “A novel asynchronous FPGA architecture design and its performance evaluation, ” International Conference on Field Programmable Logic and Applications, 2005, pp.287-292, Aug. 2005.

4. An asynchronous dataflow FPGA architecture

5. [5] D. Fang, J. Teifel, and M. Rajit, “A high-performance asynchronous FPGA: Test results, ” 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2005, FCCM 2005, pp.271-272, April 2005.

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