A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation-Reference-Cited by-同舟云学术

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A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation

Published:2011-11 Issue:11 Volume:46 Page:2500-2513
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Devlin Benjamin,Ikeda Makoto,Asada Kunihiro

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6056707/05989874.pdf?arnumber=5989874

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Investigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuits;Applied Physics Express;2024-05-01

2. A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit;2023 International Conference on IC Design and Technology (ICICDT);2023-09-25

3. Reflections on Progress in Digital Circuits: From basics to untangle past trials;IEEE Solid-State Circuits Magazine;2023

4. Advanced Devices and Architectures;Principles and Structures of FPGAs;2018

5. Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments;IEICE Transactions on Electronics;2013

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