Impact of Chip Duty Factor on DS, TH and DS-TH UWB Systems in Realistic Environment
Author:
Affiliation:
1. National Institute of Information and Communications Technology (NICT)
2. Department of Electrical and Electronic Engineering, Niigata University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E93.A/10/E93.A_10_1716/_pdf
Reference16 articles.
1. [1] Federal Communications Commission, “First report and order, revision of part no.15,” April 2002.
2. [2] Ministry of Internal Affairs and Communications of Japan (MIC), “Summary of progress on UWB technical study in Japan,” Sept. 2005.
3. [3] Electronic Communications Committee (ECC), “Report of the 11th meeting of ECC,” Sept. 2005.
4. [4] C.S. Sum, S. Sasaki, and H. Kikuchi, “The impact of chip duty factor on DS-UWB system over multipath environment in the presence of narrowband interference,” Int. Conf. on Ultra-Wideband (ICU) 2006, Massachusetts, USA, Sept. 2006.
5. [5] C.S. Sum, S. Sasaki, and H. Kikuchi, “Impact of chip duty factor in DS-UWB systems over indoor multipath environment,” IEICE Trans. Fundamentals, vol.E89-A, no.11, pp.3152-3156, Nov. 2006.
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