Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle-Reference-Cited by-同舟云学术

Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle

Published:2013 Issue:12 Volume:E96.A Page:2689-2697
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

INOUE Keisuke¹,KANEKO Mineo²

Affiliation:

1. Department of Global Information Technology, Kanazawa Technical College (KTC)

2. School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/12/E96.A_2689/_pdf

Reference11 articles.

1. [1] R. Llopis and M. Sachdev, “Low power, testable dual edge triggered flip-flops,” Proc. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp.341-345, Aug. 1996.

2. [2] C.-C. Wang, C.-C. Huang, J.-M. Huang, C.-Y. Chang, and C.-P. Lin, “ZigBee 868/915-MHz modulator/demodulator for wireless personal area network,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.16, no.7, pp.936-939, June 2008.

3. [3] C.-C. Wang, G.-N. Sung, and P.-L. Liu, “Power-aware design of an 8-bit pipelining ANT-based CLA using data transition detection,” J. Signal Process. Syst., vol.52, no.2, pp.127-135, Aug. 2008.

4. [4] C. Kim and S.-M. Kang, “A low-swing clock double-edge triggered flip-flop,” IEEE J. Solid-State Circuits, vol.37, no.5, pp.648-652, Aug. 2002.

5. [5] N. Nedovic and V.G. Oklobdzija, “Dual-edge triggered storage elements and clocking strategy for low-power systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.13, no.5, pp.577-590, May 2005.

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