A signal degradation reduction method for memristor ratioed logic (MRL) gates
Author:
Affiliation:
1. University of Chinese Academy of Sciences
2. State Key Lab of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
3. College of Computer Science and Electronic Engineering, Hunan University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/12/8/12_12.20150062/_pdf
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