Lowering Error Floors of Irregular LDPC Codes by Combining Construction and Decoding-Reference-Cited by-同舟云学术

Lowering Error Floors of Irregular LDPC Codes by Combining Construction and Decoding

Published:2012 Issue:1 Volume:E95-B Page:271-274
ISSN:0916-8516
Container-title:IEICE Transactions on Communications
language:en
Short-container-title:IEICE Trans. Commun.

Author:

JIAO Xiaopeng¹,MU Jianjun¹,FANG Fan¹,SUN Rong²

Affiliation:

1. School of Computer Science and Technology, Xidian University and Key Laboratory of Information Coding and Transmission, Southwest Jiaotong University

2. State Key Laboratory of Integrated Service Networks, Xidian University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Software

Link

http://www.jstage.jst.go.jp/article/transcom/E95.B/1/E95.B_1_271/_pdf

Reference16 articles.

1. [1] T.J. Richardson, “Error floors of LDPC codes,” Proc. 41st Annu. Allerton Conf. Commun., Contr. Comput., 2003.

2. Regular and irregular progressive edge-growth tanner graphs

3. [3] O. Fainzilber, E. Sharon, and S. Litsyn, “Decreasing error floor in LDPC codes by parity-check matrix extensions,” Proc. IEEE Intern. Symp. Inf. Theory, pp.374-378, Seoul, Korea, June 2009.

4. [4] M. Ivkovic, S.K. Chilappagari, and B. Vasic, “Eliminating trapping sets in low-density parity-check codes by using Tanner graph covers,” IEEE Trans. Inf. Theory, vol.54, no.8, pp.3763-3768, Aug. 2008.

5. [5] E. Cavus and B. Daneshrad, “A performance improvement and error floor avoidance technique for belief propagation decoding of LDPC codes,” Proc. 16th IEEE Int. Symp. on Personal, Indoor and Mobile Radio Commun., pp.3763-3768, Berlin, Germany, Sept. 2005.

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