Machine Learned Machines: Adaptive Co-optimization of Caches, Cores, and On-chip Network

Author:

Jain Rahul,Ranjan Panda Preeti,Subramoney Sreenivas

Publisher

Research Publishing Services

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A hybrid crossbar-ring on chip network topology for performance improvement of multicore architectures;International Journal of Information Technology;2023-08-31

2. Machine learning in run-time control of multicore processor systems;it - Information Technology;2023-08-01

3. Analyzing Binary Tree based Topology Configuration for Energy Efficient Multicore Architectures;2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON);2022-12-02

4. Interconnect support for energy efficient and high bandwidth memory access in CMPs;Sustainable Computing: Informatics and Systems;2022-04

5. CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance;2022 Design, Automation & Test in Europe Conference & Exhibition (DATE);2022-03-14

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