Surface Potential Modelling Based Performance Analysis of Gate Engineered Trapezoidal Trigate Tunnel FET

Abstract

In this paper, a three dimensional (3-D) analytical model of surface potential has been derived for gate engineered trapezoidal trigate Tunnel Field Effect Transistor (TFET). The model has been obtained by assuming parabolic approximation of the potential profile and solving 3-D Poisson equation using appropriate boundary conditions. The device considered in this work is silicon based TFET with gate composed of two materials with different work functions. The low work-function material is placed close to source and drain region while high work-function material is placed in between them. This will result in enhancing the tunneling in the source/channel interface region while reducing the electric field in the drain region. Trigate devices have been found to enhance the device performance at nanoscale, however, Trigate device fabricated by Intel have been found to have trapezoidal shape rather than expected rectangular shape. In this work, we have included the effect of different inclination angles of sides on the device performance. The model has been verified by comparing the results with the simulation results obtained in ATLAS software.