An Improved Area Efficient 16-QAM Transceiver Design using Vedic Multiplier for Wireless Applications

Abstract

In this research article, an improved area efficient 16-Quadrature Amplitude Modulation (QAM) transceiver design is introduced using Vedic multiplier. The 16-QAM design is transmitted using Pseudo Random Binary Sequence (PRBS) and modulated by changeable clock frequencies. The Vedic multiplier uses Urdhva Tiryakbhyam (Vertical and Crosswise) method of multiplication to reduce the undesirable steps and generates parallel partial products. Compressor adders are used in the Vedic multipliers, which helps to increase the speed of multiplication process and reduces the carry delay. Four Compressor adders namely 5-3, 10-4, 15-4 and 20-5 are used in a 16-bit Urdhva Tiryakbhyam Vedic multiplier to add its partial products. The proposed 16-QAM design is implemented using Spartan-3 XC3S200-5 pq208 Field Programmable Gate Array (FPGA) device which occupies 672 slices, 1102 4-input Look up Tables (LUTs) and 39 mW of power consumption. The Vedic multiplier based 16-QAM transceiver design reduces 17.2% slices and 4.5% 4-input LUTs. The 16-QAM is a preferred digital modulation method in the Orthogonal Frequency Division Multiplexing (OFDM) system, which reduces bit errors and noise effects during data transmission. The OFDM transceiver design is used in the high-speed wireless communication by excellence of its Multi-carrier modulation method.