Normally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration

Author:

Matsuura Kentaro,Hamada MasayaORCID,Hamada Takuya,Tanigawa Haruki,Sakamoto Takuro,Hori Atsushi,Muneta Iriya,Kawanago Takamasa,Kakushima Kuniyuki,Tsutsui Kazuo,Ogura AtsushiORCID,Wakabayashi Hitoshi

Abstract

Abstract We demonstrate chip-level integrated n-type metal–insulator–semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.

Funder

Core Research for Evolutional Science and Technology

Center of Innovation Program

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

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