MOSFET series resistance extraction at cryogenic temperatures

Abstract

Abstract A series resistance extraction method proposed recently, which uses multiple drain current versus gate voltage curves at varied drain voltages, was applied to bulk CMOS devices at low temperatures down to 4 K. A moderate reduction of series resistance compared with 300 K was found. Horizontal field dependence of mobility significantly changed with temperature, which was taken into account during the extraction. Anomalous non-linear series resistance was observed at 4 K only for p-channel FETs, suggesting the need for careful source/drain overlap design for low temperature operations.