Turn-Around of Threshold Voltage in Gate Bias Stressed p-Channel Power Vertical Double-Diffused Metal–Oxide–Semiconductor Transistors-Reference-Cited by-同舟云学术

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Turn-Around of Threshold Voltage in Gate Bias Stressed p-Channel Power Vertical Double-Diffused Metal–Oxide–Semiconductor Transistors

Published:2008-08-08 Issue:8 Volume:47 Page:6272-6276
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:en
Short-container-title:Jpn. J. Appl. Phys.

Author:

Davidović Vojkan,Stojadinović Ninoslav,Danković Danijel,Golubović Snežana,Manić Ivica,Djorić-Veljković Snežana,Dimitrijev Sima

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference34 articles.

1. Failure physics of integrated circuits — A review

2. Analysis of CMOS transistor instabilities

3. Mechanisms of positive gate-bias stress induced instabilities in CMOS transistors

4. Analysis of gamma-radiation induced instability mechanisms in CMOS transistors

5. Instabilities in MOS transistors

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1. Electrical Stress on the CMOS Inverters Made by Junctionless Gate-All-Around Transistors;IEEE Transactions on Electron Devices;2024-05

2. Temperature-Independent Gate-Oxide Degradation Monitoring of SiC MOSFETs Based on Junction Capacitances;IEEE Transactions on Power Electronics;2021-07

3. Determination of Power MOSFET’s Gate Oxide Degradation Under Different Electrical Stress Levels Based on Stress-Induced Oxide Capacitance Changes;IEEE Transactions on Electron Devices;2021-02

4. Effect of Gate-Oxide Degradation on Electrical Parameters of Power MOSFETs;IEEE Transactions on Power Electronics;2018-12

5. NBTI and irradiation related degradation mechanisms in power VDMOS transistors;Microelectronics Reliability;2018-09

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