Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory-Reference-Cited by-同舟云学术

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Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory

Published:2012-11-22 Issue:12 Volume:5 Page:121801
ISSN:1882-0778
Container-title:Applied Physics Express
language:en
Short-container-title:Appl. Phys. Express

Author:

Hung Min-Feng,Wu Yung-Chun,Tsai Tsung-Ming,Chen Jiang-Hung,Jhan Yi-Ray

Publisher

IOP Publishing

Subject

General Physics and Astronomy,General Engineering

Link

http://stacks.iop.org/1882-0786/5/i=12/a=121801/pdf

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multi-level 2-bit/cell operation utilizing Hf-based metal/oxide/nitride/oxide/silicon nonvolatile memory with HfO2 and HfON tunneling layer;Japanese Journal of Applied Physics;2022-01-13

2. Low-frequency noise in 2-bit poly-Si TANOS flash memory;Japanese Journal of Applied Physics;2014-12-16

3. A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory;Nanoscale Research Letters;2014-11-06

4. Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory;IEEE Transactions on Nanotechnology;2014-07

5. Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory;Nanoscale Research Letters;2013-07-22

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