Author:
Pang Liang-Teck,Nikoli´c Borivoje
Reference26 articles.
1. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
2. B. Nikolic and L.T. Pang, Measurements and analysis of process variability in 90 nm CMOS, 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 505-508, 2006.
3. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
4. P. Oldiges, Qimghuamg Lin, K. Petrillo, M. Sanchez, M. Ieong, and M. Hargrove, Modeling line edge roughness effects in sub 100 nm gate length devices, SISPAD 2000, 131,2000.