(Invited) 3D Packaging Technologies and Applications, Latest Challenges and Supply Chain Activities

Abstract

Semiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging solutions, considered today the most advanced technology, that could enable various heterogeneous integration. 3D Integration is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore.