1. S. Casimirus , inSymposium Proceedings of 3-D Chip Stacking, K. Kondo , Editor, p.106, The Electronics Division of Chemical Engineering, Japan, Tokyo (2009).
2. ASET, Annual Reports of Electronics SI (1999, 2000).
3. K. Takahashi, Y. Taniguchi, M. Tomisaka, H. Yonemoto, M. Hoshino, M. Ueno, E. Egawa, Y. Nemoto, T. Yonezawa, and K. Kondo ,Electronic Components & Technology Conference, ASET and Okayama University, p. 601 May, Las Vegas (2004).
4. High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking
5. High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking