Charge Trapping in High-k Gate Dielectrics: A Recent Understanding

Abstract

Charge trapping in Hf-based high-k dielectrics, used in MOS transistor gate stacks, causes threshold voltage shift during constant voltage stress (CVS). It seemed to be very transient due to the presence of a large number of shallow traps and can be eliminated by applying a reverse direction electric field. Recent findings, however, suggest that deep traps significantly contribute to the reliability of various Hf- based high-k gate stacks. The origin of the deep traps and their dependence on O vacancy formation during dielectric deposition is discussed. Flatband shift and leakage current dependence on these deep traps is also outlined. We have experimentally observed trap levels from low temperature measurements assuring the presence of O vacancies in Hf- silicate based films. It is further shown that negative-U transition to deep defects is responsible for trap assisted tunneling under substrate injection. This has the potential to be the ultimate limiting factor for the long-term reliability of Hf-based high-k gate dielectrics.