Reducing Formation Time of the Inversion Layer by Illumination around a Memory Capacitor

Abstract

Capacitor structures are often used to evaluate the program and erase characteristics of charge trapping memory devices. Due to thermally generation of a few minority carriers, the operation efficiency of memory devices is underestimated for the weak response to the formation of inversion layer. In this paper, illumination around a memory capacitor is introduced. Experiment results show that illumination reduces the formation time of the inversion layer and thus increase the program/erase efficiency. Thereby, it is more accurate to characterize program/erase transients of memory devices with capacitor structures under illumination.