Advanced Electrochemical Processes for Sub-50 nm On-chip Metallization

Abstract

Additives-assisted electrodeposition on a PVD copper seed is capable of generating void-free 'bottom-up' fill in vias and trenches with moderate aspect ratios (~10:1). For future generation copper interconnects, scaling causes the via and trench aspect ratios to increase, i.e., dual damascene aspect ratios larger than 10:1 due to the overhang caused by the PVD copper seed. For filling such aggressive geometries, advanced electroplating additives which provide improved suppression/acceleration properties need to be developed. In the present work, several gap-fill strategies for sub-50nm technology node will be outlined including: (i) Development and characterization of advanced electroplating additives, and (ii) Direct plating of copper on novel liner metals (e.g., Ru). Scaling of copper interconnects also necessitates improved electromigration resistance. Electroless Co caps will be discussed as a potential solution for improving reliability of sub-50nm copper interconnects.