Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors-Reference-Cited by-同舟云学术

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Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

Published:2021-10-01 Issue:4 Volume:104 Page:217-227
ISSN:1938-5862
Container-title:ECS Transactions
language:
Short-container-title:ECS Trans.

Author:

Durfee Curtis,Kal Subhadeep,Pancharatnam Shanti,Bhuiyan Maruf,Otto IV Ivo,Flaugh Matthew,Smith Jeffrey,Chanemougame Daniel,Alix Cheryl,Zhou Huimei,Frougier Julien,Greene Andrew,Belyansky Michael,Watanabe Koji,Zhang Jingyun,Schmidt Daniel,Breton Mary,Zhao Kai,Wang Miaomiao,Basker Veeraraghavan,Mosden Aelan,Loubet Nicolas,Guo Dechao,Biolsi Peter,Haran Bala,Bu Huiming

Publisher

The Electrochemical Society

Link

https://iopscience.iop.org/article/10.1149/10404.0217ecst/pdf

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology;Nanomaterials;2024-05-09

2. From lab to fab: in-line SIMS for process control in nanosheet gate-all-around device manufacturing;Metrology, Inspection, and Process Control XXXVIII;2024-04-10

3. Study of precisely controlled selective isotropic quasi-ALE of SiGe;Advanced Etch Technology and Process Integration for Nanopatterning XIII;2024-04-09

4. Development of SiGe Indentation Process Control for Gate-All-Around FET Technology Enablement;IEEE Transactions on Semiconductor Manufacturing;2022-08

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