III-V/Ge Channel Engineering for Future CMOS

Abstract

As silicon CMOS reaches its scaling limits, alternative materials become more attractive. Dielectric thickness and parasitic resistance and capacitance do not scale well, so "more than Moore" scaling is required even to keep up with Moore's Law. Replacing Si MOSFET channels on a short time scale (3-6 years) raises significant challenges for any proposed material or device structure. New materials must be compatible with Si CMOS fabrication. In(1-x)Ga(x)As based MOSFETs offer higher carrier velocities than Si, plus contact resistivities below 1E-8 ohm-cm^2, mature processing, and straightforward heterostructure confinement for vertical scaling, and additional degrees of freedom in composition and heterostructure for future scaling. Self-aligned source-drain regrowth places contact metal within 30 nm of the channel, reducing access resistance. Here we demonstrate InGaAs channels with self-aligned regrowth of source/drain contacts. This work led to depletion mode InGaAs MOSFETs with peak transconductance of 0.24 mS/micron.