(Invited) Stress Simulations of Si- and Ge-Channel FinFETs for the 14 nm-Node and Beyond

Abstract

This work studies the effectiveness of stressors for Si- and Ge-channel gate-last FinFETs in nested layouts with dimensions of the 14, 10 and 7 nm-nodes. P-type FinFETs with Si-channels can be efficiently boosted by SiGe source/drain (S/D) stressors, and provide higher mobility than relaxed Ge-channel pFinFETs. The highest pFET mobility is found for strained Ge-channels: in this case a SiGe Strain-Relaxed Buffer (SRB) with Ge < 90% leads to a channel mobility that is significantly higher than what is achievable with strained Si. For nFETs, a SiGe-SRB is the most efficient booster for Si-channels. Theoretically, the electron mobility of Ge fin sidewalls is very high, making Ge-channel nFinFETs a promising alternative, even without strain. SRBs are the most efficient stressors and are scalable beyond the 14 nm-node. Etching the fins in the S/D regions releases strain generated by the SRB, therefore raised S/D stressors are preferred over recessed for maximal mobility when combined with SRBs. Except for SRBs and S/D stressors, the other stressors studied in this work (contact etch-stop layers, stressed gates and contacts) are found to be inefficient in nested 14 nm-node layouts.