28nm Overlay Control Improvement By Wafer Quality Enhancement and Mask Registration Control

Abstract

It is known that critical dimension (CD), overlay, and defect are the three most crucial factors for Semi-conductor manufacture. Overlay control is especially important for Gate layer. In this paper we will focus on how to control overlay performance. Simulation will be carried out to optimize under-layer films to optimize the alignment signal strength, or the ASML’s unit: wafer quality (WQ). A solid alignment can ensure a good overlay control. Mask registration can also affect overlay performance markedly which is a new learning at 28nm tech node. A simple error distribution from metrology measurement angel will be made to discuss the effect of mask registration to overlay performance. KLA SOV (sources of variation) tool will be used to trace the error sources and analyze how much they each contribute to the total overlay error. Finally, a specification on mask registration error is built based on this analysis. Through these improvements, ITRS referred overlay specification is achieved on ASML immersion scanner. We believe that with high order function turned on, even better overlay performance will be achieved which could meet the manufacturing tolerances for the 28nm technology node.