1. ITRS 2012 update, http://www.itrs.net/Links/2012ITRS/Home2012.htm
2. Towards 3nm overlay and critical dimension uniformity: An integrated error budget for double patterning lithography;Arnold,2008
3. Impact of Process Decisions and Alignment Strategy on Overlay for the 14nm Node;David Laidler,2013
4. 28nm Overlay Control Improvement By Wafer Quality Enhancement and Mask Registration Control
5. In-Die Mask Registration Measurement on 28nm Node and Beyond;Chen,2013