A Dual-Drain Vertical Tunnel FET with Improved Device Performance: Proposal, Optimization, and Investigation

Abstract

In this manuscript, a dual-drain Vertical Tunnel FET structure is proposed and investigated for the first time. The simulation outcomes clearly manifest that reduction in channel thickness, which has inadequate impact on the tunneling region, significantly improves numerous DC parameters of the proposed device including subthreshold swing, on-state current and current-switching ratio by enhancing the band-to-band tunneling of the charge carriers at source/channel interface caused by enlarged electric field. In order to make the proposed device suitable for low power applications, dielectric material is incorporated in between two drain/channel interfaces to reduce the subthreshold leakage current. A detailed investigation is carried out to determine the influence of varying device footprints on various electrical parameters and accordingly, the optimized device performance is achieved. TCAD-based simulation results reveal that a considerably low subthreshold swing of 18 mV decade−1 along with a high current-switching ratio of 1.6 × 10 13 can be achieved with optimum geometric dimension of design parameters i.e., gate-oxide, source and channel. Further, the performance of the proposed device is compared with various existing TFET structures and found to be superior in terms of current switching ratio, average subthreshold swing and turn-on voltage. The probable fabrication process flow is also discussed for the proposed device and based on the proper benchmarking, it is revealed that improvement in the parameters like low-output voltage, peak overshoot and rise time defining the switching characteristics of an inverter makes the proposed device more suitable for digital circuit-based applications.