The Impact of Back-Side Cu Contamination on 3D Stacking Architecture-Reference-Cited by-同舟云学术

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The Impact of Back-Side Cu Contamination on 3D Stacking Architecture

Published:2010 Issue:2 Volume:13 Page:H39
ISSN:1099-0062
Container-title:Electrochemical and Solid-State Letters
language:en
Short-container-title:Electrochem. Solid-State Lett.

Author:

Yang Yu,Labie Riet,Richard Olivier,Bender Hugo,Zhao Chao,Verlinden Bert,De Wolf Ingrid

Publisher

The Electrochemical Society

Subject

Electrical and Electronic Engineering,Electrochemistry,Physical and Theoretical Chemistry,General Materials Science,General Chemical Engineering

Reference15 articles.

1. A wafer-scale 3-D circuit integration technology

2. Physics of Copper in Silicon

3. Copper Behavior in Bulk Silicon and Associated Characterization Techniques

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1. Study on Room-Temperature Wet Oxidation of Silicon Catalyzed by Copper;Langmuir;2023-01-03

2. Impact of Metals on Silicon Devices and Circuits;Metal Impurities in Silicon- and Germanium-Based Technologies;2018

3. A Detailed Failure Analysis Examination of the Effect of Thermal Cycling on Cu TSV Reliability;IEEE Transactions on Electron Devices;2014-01

4. Cu Contamination of the nMOSFET in a 3-D Integrated Circuit under Thermal and Electrical Stress;Electrochemical and Solid-State Letters;2012

5. Low-Frequency Noise Assessment of CMOS Transistors with a Through-Silicon Via;ECS Transactions;2011-10-04

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