Decreasing the Off-Current for Vertical TFT by Using an Insulating Layer between Source and Drain

Abstract

A novel polysilicon vertical thin film transistor (VTFT) has been fabricated based on a low-temperature (T{less than or equal to}600{degree sign}C) process. This new structure eliminates the large overlapping area between source and drain, and thus reduced the off-current and increased the Ion/Ioff ratio. The technologically key point lies in the introduction of an insulating layer between source and drain, and the electrical properties of the fabricated VTFTs using different insulating layers are compared. These first results highlight that the SiO2 insulating layer shows great advantages over the Si3N4 insulating layer. The reduced off-current has revealed some potential applications for high density integration and high drive current.