(Invited) Integration and Scalability of ALD-Based Mixed Phase Nanometer-Scale Barrier Layers for Extendable Metal Interconnects

Abstract

The sub-22nm CMOS device regime represents the introduction of significant challenges to conventional copper-based interconnect fabrication. In particular, the scalability of PVD-based copper barrier and seed methodologies for future interconnects is not assured. Alternative material and processing strategies based on directly-platable barriers formed by atomic layer deposition-based processing techniques hold promise to enable continued performance extendibility of copper interconnects. This paper will discuss a number of approaches under consideration, and will describe the mechanisms that allow these approaches to achieve performance targets for sub-22nm interconnects.