High Field Induced Stress Suppression of GIDL Effects in Accumulation-Mode P-Channel TFTs

Abstract

By utilizing the effects of high energy, or "hot", electrons the GIDL current in an accumulation mode thin-film PFET can be suppressed. Both SOI and single crystal silicon-on-glass (SiOG) substrates were used to examine this effect. This suppression is proposed to be due to local injection of charge into the gate-oxide at the drain end of the transistor creating a mirror charge in the silicon which mimics an asymmetrical lightly-doped drain structure. An overview of theory, modeling, and device characterization is presented in this study. This effect has been shown to be stable and reproducible; a technique to measure the location and quantity of injected charge is under development.