Interface and Border Traps in Ge-Based Gate Stacks

Abstract

A critical issue for the successful integration of Ge devices into future high-performance technology nodes is the electrical passivation of the Ge surface. We have examined this electrical passivation in terms of interface and border traps for several Ge-based gate stacks, where we varied amongst others the GeO2 thickness, the high-k material and the Post Deposition Anneal (PDA). The GeO2 thickness seems to have the largest impact, and an inverse relation between the density of interface traps Dit and border traps Nbt exists for GeO2 layers up to ~2 nm. We found that the most optimal passivation is achieved by using an (almost) oxide-free surface as this would result in the lowest Nbt. Although such a surface is characterized by a high mid-gap Dit, this can be improved by performing the correct PDA. We conclude that the most promising oxide-free surface is obtained after an H2S treatment.