Slow Trap Properties and Generation in Al2O3/GeOx/Ge MOS Interfaces Formed by Plasma Oxidation Process
Author:
Affiliation:
1. Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan
Funder
Core Research for Evolutional Science and Technology
Ministry of Education, Culture, Sports, Science and Technology
Publisher
American Chemical Society (ACS)
Subject
Materials Chemistry,Electrochemistry,Electronic, Optical and Magnetic Materials
Link
https://pubs.acs.org/doi/pdf/10.1021/acsaelm.8b00071
Reference33 articles.
1. Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs
2. Improved Electrical Properties of Ge p-MOSFET With $ \hbox{HfO}_{2}$ Gate Dielectric by Using $\hbox{TaO}_{x} \hbox{N}_{y}$ Interlayer
3. High performance germanium MOSFETs
4. Gate dielectric formation and MIS interface characterization on Ge
5. First-principles study to obtain evidence of low interface defect density at Ge/GeO2 interfaces
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