A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs

Abstract

This paper introduces an Overlapping Circular-Gate Transistor (O-CGT) that allows gate overlaying between neighboring cells, enhancing layout packing with respect to conventional circular- and rectangular-gate structures. Although a section of gate annulus does not contribute to the drain current, a higher aspect-ratio is attained. Besides, both drain and source junctions have their area minimized, so that faster transients can be reached. A first-order model for the effective aspect-ratio of the proposed device is developed and its validity attested by a range of 3D-simulation of IDS x VDS characteristics obtained with ATLAS3D software. Error between analytical and 3D-simulation data was limited to only 4.7%, for different VGS values. With respect to a conventional circular-gate transistor (CGT), the O-CGT breakdown voltage BVDS is reduced by a factor of only 6.1%. A power FET with on-resistance in the interval of tens of mOhms is laid out having the O-CGT as elementary cell. To verify the benefits of the O-CGT, a comparison with a rectangular-geometry transistor (RCT) is carried out. Defining a figure-of-merit as n= (W/L)/cell_area, the O-CGT features a better efficiency on current driving capability, as nO-GCT/ nRCT = 22.9%. Unity cell size, drain and source junction areas are reduced by factors of 81.3%, 33.9% and 40.6%, respectively. The O-CGT approach allows a saving of 18.6% in the power FET size as compared to rectangular geometries.