Abstract
This paper describes wafer-on-wafer (WOW) technology using bumpless through-dielectrics-silicon-via (TDSV) and dual-damascene interconnects for three-dimensional integration (3DI). Trends in conventional scaling compared with bumpless processes, the characteristics of devices after thinning the wafers to less than 10 um, and applications, including closed-channel-cooling systems (C3S), are discussed.
Publisher
The Electrochemical Society
Cited by
4 articles.
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