Extraction of Trap Parameters for High-Κ Gate Stacks

Abstract

A small-signal steady state admittance technique, containing some new approaches, is outlined in this paper, for the extraction of the trap parameters, such as the trap density, the trap-energy, and the trap-capture-cross-section/trap-location in the direction perpendicular to the interface, for high-K gate stacks. This technique also yields the experimental values of the total gate-dielectric-stack capacitance, the flat-band voltage, and the surface potential. This technique is applied to p-Si/SiO2/HfO2/TaN MOS capacitors, and the results are presented and analyzed.