1. International Technology Roadmap for Semiconductors, 2003 ed., Semiconductor Industry Association, San Jose, CA (2003).
2. W. Lerch, S. Paul, D.F. Downey, and E.A. Arevalo , inAdvanced Short-Time Thermal Processing for Si-Based CMOS Devices, F. Roozeboom , E, Gusev , L.-J. Chen , , D.-L. Kwong , and P. J. Timans , Editors, PV 2003-14, p. 43, The Electrochemical Society Proceedings Series, Pennington, NJ (2003).
3. S. Paul, W. Lerch, D.F. Downey, and E.A. Arevalo ,Workshop on Ultra-shallow Junction Formation, USJ 2003, April 27–May 1, 2003, p. 111, Santa Cruz, CA (2003).
4. Silicon deposition from BCl[sub 3]/SiH[sub 4] mixtures: Effect of very high boron concentration on microstructure
5. W. Lerch, B. Bayha, D.F. Downey, and E.A. Arevalo , inRapid Thermal and Other Short-Time Processing Technologies II, D.-L. Kwong , K. G. Reid , M. C. Öztürk , P. J. Timans , and F. Roozeboom , Editors, PV 2001-9, p. 321, The Electrochemical Society Proceedings Series, Pennington, NJ (2001).