Texture and Grain Size Investigation in the Copper Plated Through-Silicon via for Three-Dimensional Chip Stacking Using Electron Backscattering Diffraction-Reference-Cited by-同舟云学术

Texture and Grain Size Investigation in the Copper Plated Through-Silicon via for Three-Dimensional Chip Stacking Using Electron Backscattering Diffraction

Published:2011 Issue:5 Volume:14 Page:D48
ISSN:1099-0062
Container-title:Electrochemical and Solid-State Letters
language:en
Short-container-title:Electrochem. Solid-State Lett.

Author:

Kadota Hiroyuki,Kanno Ryuichi,Ito Masahiko,Onuki Jin

Publisher

The Electrochemical Society

Subject

Electrical and Electronic Engineering,Electrochemistry,Physical and Theoretical Chemistry,General Materials Science,General Chemical Engineering

Reference13 articles.

1. H. Yonemura, M. Tomisaka, M. Hoshino, K. Takahashi, and H. Kadota , in Proceedings of ADMETA Conference , NEDO, pp. 40–41 (2002).

2. S. Denda , TSV Technique for Three-dimensional Integration , pp. 1–77, Kogyo Chosakai Publishing Co., Ltd., Japan (2009) (in Japanese).

3. K. Kondo, Y. Suzuki, T. Saito, and N. Okamoto , Abstract 2180, The Electrochemical Society Meeting Abstracts, Vol. 902, Vienna, Austria, Oct 4–9, 2009.

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