(Invited) High Accuracy Aligned Wafer Bonding for Wafer-Level Integration

Abstract

Direct wafer bonding for SOI substrates manufacturing was probably the first volume production application based on bonding. As this application involves bonding of two non-patterned substrates the requirements for wafer-to-wafer alignment accuracy were very loose: mechanical (edge-to-edge) alignment with accuracies in the range of 50-100 µm was absolutely sufficient. For applications using other wafer bonding processes (the first sensors that were manufactured using glass frit bonding and anodic bonding) such rough alignment methods were still usable but in parallel optical alignment was adopted: in this case the alignment accuracy needs were going down to 5 – 20 µm. The increased device complexity of the applications which could benefit from wafer bonding advantages required for features from the bonding partners to be aligned to each other (either functional parts of the devices or structures necessary for the successful bonding process, such as bonding lines on both wafers): in such cases optical alignment became necessary and the technology progress was reflected also in more demanding requirements for the wafer-to-wafer optical alignment. For the early generations of these applications the required accuracy was still low, so it was possible to use adapted photolithography mask aligners. Later on, with higher accuracy requirements dedicated bond alignment systems were introduced in order to meet the tighter alignment specifications. With the adoption of direct (fusion) wafer bonding for backside illuminated (BSI) CMOS image sensors initially for consumer electronics this process found its way into the integration flow. For this application the device performance can be significantly improved by increasing the level of integration with the electronic components. For the first generations of devices the alignment accuracy was still not critical as one of the two substrates to be bonded did not have any electrically functional structures and optical alignment was required in order to guarantee a high yield for the patterning steps following the direct bonding and thinning of the CMOS image sensors wafer. This new application introduced a new requirement for direct bonding which was not considered before: besides the required alignment precision the need to simultaneously control the local wafer stress and deformation during the bonding process became crucial, as it leads to remaining distortion of the image sensor wafers. Patterns distortion causes problems with color filter manufacturing by subsequent stepper photolithography and ends up in cross talk between different colors. Especially for mobile devices the image sensors keep shrinking and combined with increasing the resolution at the same time the pixel sizes have reached levels where distortion levels below 50 nm are necessary. With further development of these image sensors also the second bonding partner wafer moved from the carrier wafer functionality to electrically active structures which required electrical connection to the image sensor wafer. Different integration schemes were developed, such as via last connection after the bonding where one wafer is thinned, vias are formed, which are subsequently filled with metal in order to achieve electrical connections. This paper aims to present an overview of the existing wafer-to-wafer alignment technology. The development of optical alignment methods will be reviewed with respect to applications requirements evolution over time. An overview of the different factors contributing to the overall misalignment budget and how they are controlled now or will be in the future in order to meet the stringent requirements will be presented with examples.