(Invited) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling

Abstract

We report on vertically stacked nanosheet (NS) FET devices as the most promising candidates to replace finFETs, discussing some of their key features and potential extension and/or alternative options to help preserve the power, performance, area, and cost (PPAC) logic roadmap for advanced sub-5nm technology nodes, being also attractive for cold computing. In addition, given the increased complexity and cost in back-end-of-line processing, to take full advantage of the scaling performance benefits at transistor level it has also become ever more pressing to address signal and power wiring bottlenecks. The concept of moving power delivery to the wafer’s backside has been gaining traction and we will thus also explore it in this work by combining logic and 3D technologies and assess its feasibility by evaluating the impact of 3D processing on device characteristics.