(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions

Abstract

We report on vertical tunnel field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions. III-V nanowire (NW) was heterogeneously integrated on Si by selective-area growth with precise positioning. The III-V NW/Si heterojunction consisting of a few misfit dislocations shows a large Zener tunnel current under positive bias and band-to-band tunneling current under forward bias. The vertical TFET using InGaAs NW/Si heterojunction, which is vertical surrounding-gate architecture, demonstrated a steep turn-on behavior and very low parasitic leakage current.