Impact of Metallic Contamination on Si: Shortloop Issues

Abstract

Advanced Integrated Circuit (IC) manufacturing faces both the development of many products and the introduction of a large number of new materials, which represent possible risk of contamination. Therefore, the estimation of the dangerousness of metallic elements must be estimated by relevant short loops. The process steps used in the short loop should represent the production reality or should be performed in the most detrimental conditions. This study shows the impact of different short loop parameters on the dangerousness of metallic elements and their behaviour toward Si and SiO2: type of contamination (depending on the deposition method), thermal budget, oxidizing and non oxidizing atmosphere of the intra-diffusion step, metrology technics. This paper shows that the usual short loops fulfil the conditions of a relevant test. Accordingly, estimation of the dangerousness of the metallic elements can be used to determine detrimental thresholds in manufacturing areas.